This invention relates to a computer system comprising a main memory for memorizing main data and a cache memory for memorizing selected data of the main data. More particularly, this invention relates to an apparatus used in the computer system for carrying out an operation for accessing to the main memory when a desired datum of the main data is not memorized as one of the selected data in a particular address of the cache memory.
Such a computer system comprises a processing unit connected to the cache memory. When it is required to read the desired datum, the processing unit produces a cache access signal. Responsive to the cache access signal, the cache memory sends the desired datum to the processing unit when the desired datum is memorized in the cache memory.
When the desired datum is not memorized in the cache memory, the cache access signal is modified into an actual address signal representative of an actual address of the main memory. The actual address signal serves to access to the main memory.
An architecture computer system is known in the art. The architecture computer system is classified into a first and a second type. In the first type, each main datum comprises only a data part and has a first data length. In the second type, each maid datum comprises the data part and a tag part and has a second data length. The system of the second type is generally called a tagged architecture computer system.
In a particular case where the data part in the first type has a predetermined length which is equal to that of the data part in the second type, it is a matter of course that the first and the second data lengths are different from one another. Therefore, consistency can be obtained between the first and the second types in the particular case. More particularly, it is impossible to exchange the main data between the first and the second types. In other words, the computer system of the second type can not use a main memory of the computer system of the first type.